1. Field of the Invention
The field of the invention is semiconductor processing. More specifically, the invention relates to reducing foreign material concentrations in a semiconductor process.
2. Background of the Invention
In the fabrication of a semiconductor device, using conductive lines or interconnects having low resistance to electrical flow for transmitting electrical signals to and from the semiconductor device increases the speed of the semiconductor device. In order to achieve low resistance values for the interconnects, highly conductive metals such as aluminum or copper are used. The interconnects are surrounded by a dielectric material, such as silicon oxide, in order to provide electrical isolation between the interconnects. In one process technique known as the damascene process, the silicon oxide dielectric layer is formed and is then patterned using known photolithography and etch techniques to provide trenches or holes in the silicon oxide dielectric. A plasma clean using an inert gas such as an argon sputter clean is performed to clean the underlying surface exposed by a trench or hole, such as an underlying metal interconnect or a via surface. The interconnect metal is deposited into the trench or hole and planarized to a top surface of the silicon oxide dielectric. The plasma clean provides for a clean underlying surface that reduces electrical contact resistance between the deposited interconnect metal and the underlying surface further improving the speed performance of the semiconductor device.
Since the dielectric layer is at least partially exposed during the plasma clean process, reaction products of the dielectric layer form on exposed surfaces of the plasma clean reaction chamber, such as chamber walls and portions of the substrate holder. A plasma clean reaction chamber such as, for example, a sputter etch chamber, includes a base having a substrate holder for holding a substrate during processing and a quartz dome which encloses the substrate holder and forms the process volume for the plasma clean reaction to occur. For a substrate having a silicon oxide dielectric layer exposed to an argon sputter clean, silicon oxide reaction products such as Si and SiOx are formed on the exposed surfaces of the sputter etch chamber. It has been found that for semiconductor substrates in a 0.13 um technology, the silicon oxide reaction products adhere to the exposed surfaces of the sputter etch chamber with sufficient strength such that an average of about 2000 semiconductor substrates can be processed prior to significant portions of the silicon oxide reaction products detaching from the sputter etch chamber walls and exposed surfaces resulting in foreign material contamination of subsequently processed semiconductor substrates. Processing of the semiconductor substrates in the sputter etch chamber is stopped and the sputter etch chamber is removed from production for chamber cleaning. Chamber cleaning includes venting the sputter etch chamber to atmospheric pressure and removing the quartz dome. Silicon oxide reaction products adhering to the quartz dome and exposed surfaces of the sputter etch chamber are removed by physical and chemical techniques such as bead blasting the inner surface of the quartz dome followed by a water rinse and wiping with isopropyl alcohol (IPA). After the components of the sputter etch chamber have been cleaned, the chamber is re-assembled, pumped down to vacuum, conditioned and returned to production.
The increasing demands of semiconductor applications has resulted in the need for further improvement in the speed and size of semiconductor devices. The dielectric layer used to electrically insulate metal interconnects introduces a parasitic dielectric capacitance into the semiconductor device. As the distance between metal interconnects decreases as semiconductor devices become smaller, the parasitic dielectric capacitance increases resulting in a degradation of the speed of semiconductor devices. Silicon oxide has been used as the dielectric layer due to its relatively easy integration into existing semiconductor processing technology. However, as semiconductor devices continue to decrease in size, the increasing parasitic dielectric capacitance introduced by a silicon oxide dielectric layer becomes a significant factor in reducing the speed of semiconductor devices.
The insulating properties of a dielectric material can be characterized by a relative value, known as the “K” value of the dielectric material. For example, air is a high electrically insulating dielectric and is assigned a “K” value of 1.0. By comparison, silicon oxide is less electrically insulating than air and has a higher “K” value of approximately 4.5. A high “K” value is an indication of a relatively lower electrical insulating property of a dielectric material. As the requirements for semiconductor devices demand decreases in size and increases in speed, dielectric materials having a “K” value less than silicon oxide are desired in order to reduce the parasitic dielectric capacitance. Dielectric materials such as “Silicon Low-K” (hereinafter referred to as SiLK) available from Dow Chemical Co., “Black Diamond” available from Applied Materials Inc. or “Coral” available from Novellus Corp., have “K” values ranging from about 3.5 to about 2.0 or lower which make them candidates to replace silicon oxide as a dielectric layer in semiconductor devices. “Low K” dielectric materials such as SiLK are formed of polymers and contain carbon. SiLK can be used to replace silicon oxide as the interconnect dielectric layer in semiconductor devices resulting in a reduction of the parasitic dielectric capacitance.